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TP3054-X Datasheet(PDF) 7 Page - Texas Instruments |
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TP3054-X Datasheet(HTML) 7 Page - Texas Instruments |
7 / 22 page TP3054-X, TP3057-X www.ti.com SNOSBY2C – MARCH 2005 – REVISED APRIL 2013 Timing Specifications Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC = +5.0V, VBB = –5.0V, TA = 25°C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 1/tPM Depends on the Device Used and the 1.536 MHz Frequency of Master Clocks BCLKR/CLKSEL Pin. 1.544 MHz MCLKX and MCLKR 2.048 MHz tRM Rise Time of Master Clock MCLKX and MCLKR 50 ns tFM Fall Time of Master Clock MCLKX and MCLKR 50 ns tPB Period of Bit Clock 485 488 15725 ns tRB Rise Time of Bit Clock BCLKX and BCLKR 50 ns tFB Fall Time of Bit Clock BCLKX and BCLKR 50 ns tWMH Width of Master Clock High MCLKX and MCLKR 160 ns tWML Width of Master Clock Low MCLKX and MCLKR 160 ns tSBFM Short Frame 100 ns Set-Up Time from BCLKX High First Bit Clock after the Leading Edge of to MCLKX Falling Edge FSX Long Frame 125 tSFFM Setup Time from FSX High to 100 ns Long Frame Only MCLKX Falling Edge tWBH Width of Bit Clock High VIH=2.2V 160 ns tWBL Width of Bit Clock Low VIL=0.6V 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time from Frame Sync Long Frame Only 115 ns to Bit Clock Low tDBD Delay Time from BCLKX High Load=150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid tDBTS Delay Time to TSX Low Load=150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLKX Low to CL=0 pF to 150 pF 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from FSX or BCLKX, Whichever CL=0 pF to 150 pF 20 165 ns Comes Later tSDB Set-Up Time from DR Valid to 50 ns BCLKR/X Low tHBD Hold Time from BCLKR/X Low to 50 ns DR Invalid tSF Set-Up Time from FSX/R to Short Frame Sync Pulse (1 Bit Clock Period Long) 50 ns BCLKX/R Low tHF Hold Time from BCLKX/R Low Short Frame Sync Pulse (1 Bit Clock Period Long) 100 ns to FSX/R Low tHBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit Clock Periods Bit Clock Low to Frame Sync 100 ns Long) (FSX or FSR) tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level) Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TP3054-X TP3057-X |
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