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INA110AG Datasheet(PDF) 8 Page - Texas Instruments |
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INA110AG Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 21 page  INA110 8 SBOS147A www.ti.com DISCUSSION OF PERFORMANCE A simplified diagram of the INA110 is shown on the first page. The design consists of the classical three operational amplifier configuration using current-feedback type op amps with precision FET buffers on the input. The result is an instrumentation amplifier with premium performance not normally found in integrated circuits. The input section (A1 and A2) incorporates high perfor- mance, low bias current, and low drift amplifier circuitry. The amplifiers are connected in the noninverting configura- tion to provide high input impedance (1012 Ω). Laser-trim- ming is used to achieve low offset voltage. Input cascoding assures low bias current and high CMR. Thin-film resistors on the integrated circuit provide excellent gain accuracy and temperature stability. The output section (A3) is connected in a unity-gain differ- ence amplifier configuration. Precision matching of the four 10kΩ resistors, especially over temperature and time, assures high common-mode rejection. BASIC POWER SUPPLY AND SIGNAL CONNECTIONS Figure 1 shows the proper connections for power supply and signal. Supplies should be decoupled with 1 µF tantalum capacitors as close to the amplifier as possible. To avoid gain and CMR errors introduced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. Resistance in series with the reference (pin 6) will degrade CMR. To maintain stability, avoid capacitance from the output to the gain set, offset adjust, and input pins. INA110’s input (RTI) is the offset of the input stage plus the offset of the output stage divided by the gain of the input stage. This allows specification of offset independent of gain. FIGURE 2. Offset Adjustment Circuit. 1 2 6 10 INA110 9 V OUT 100k Ω 4 –V CC 5 14 15 100k Ω +V CC Input Offset Adjust Output Offset Adjust ∆V IN For systems using computer autozeroing techniques, neither offset nor offset drift are of concern. In many other applica- tions, the factory-trimmed offset gives excellent results. When greater accuracy is desired, one adjustment is usually sufficient. In high gains (>100) adjust only the input offset, and in low gains the output offset. For higher precision in all gains, both can be adjusted by first selecting high gain and adjusting input offset and then low gain and adjusting output offset. The offset adjustment will, however, add to the drift by approximately 0.33 µV/°C per 100µV of input offset voltage that is adjusted. Therefore, care should be taken when considering use of adjustment. Output offsetting can be accomplished as shown in Figure 3 by applying a voltage to the reference (pin 6) through a buffer. This limits the resistance in series with pin 6 to minimize CMR error. Be certain to keep this resistance low. Note that the offset error can be adjusted at this reference point with no appreciable degradation in offset drift. FIGURE 3. Output Offsetting. 1 6 10 INA110 9 V OUT R 3 OPA177 ∆V IN V OUT = VOFFSETTING + ∆VIN G. R 2 R 1 +V CC –V CC V OFFSETTING V OFFSETTING With ±V CC = 15V, R1 = 100kΩ, R2 = 1MΩ. R 3 = 10kΩ, VOFFSETTING = ±150mV. 2 OFFSET ADJUSTMENT Figure 2 shows the offset adjustment circuit for the INA110. Both the offset of the input stage and output stage can be adjusted separately. Notice that the offset referred to the FIGURE 1. Basic Circuit Connection. 1 13 12 16 11 3 2 8 6 10 9 V OUT ∆V IN x10 x100 x200 x500 7 1µF R L –V CC 1µF +V CC Sense V OUT = ∆VIN G INA110 |
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