K4S561633C-R(B)L/N/P

Rev. 1.4 Dec. 2002

CMOS SDRAM

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Parameter

Symbol

- 75

-1H

-1L

Unit

Note

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS latency=3

7.5

1000

9.5

1000

9.5

1000

ns

1

CAS latency=2

9.5

9.5

12

CAS latency=1

-

-

25

CLK to valid output delay

CAS latency=3

5.4

7

7

ns

1,2

CAS latency=2

7

7

8

CAS latency=1

-

-

20

Output data hold time

CAS latency=3

2.5

2.5

2.5

ns

2

CAS latency=2

2.5

2.5

2.5

CAS latency=1

-

-

2.5

CLK high pulse width

2.5

3

3

ns

3

CLK low pulse width

2.5

3

3

ns

3

Input setup time

2.0

2.5

2.5

ns

3

Input hold time

1.0

1.5

1.5

ns

3

CLK to output in Low-Z

1

1

1

ns

2

CLK to output in Hi-Z

CAS latency=3

5.4

7

7

ns

CAS latency=2

7

7

8

CAS latency=1

-

-

20

Note :

1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life

is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of

a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea

repeater use.