TPS3513

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SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

FPO

3

O

Inverted fault protection output, open-drain, output stage.

A low level indicates that the fault is not latched, while floating indicates that the fault is latched.

GND

2

Ground

IS12

5

I

12-V overcurrent protection

IS5

8

I

5-V overcurrent protection

IS33

9

I

3.3-V overcurrent protection

NC

7

No internal connection

PGI

1

I

Power-good input.

A low level indicates that power is not good, while a high (>1.2V) indicates that power is good.

PGO

14

O

Power-good output, open drain output stage.

A low level indicates that power is not good, while floating indicates that power is good.

PSON

4

I

On/off control.

Pull low to enable the PC Power Supply; float to disable it.

RI

6

I

Current sense setting

13

I

Supply voltage

VS12

10

I

12-V overvoltage/undervoltage protection

VS33

11

I

3.3-V overvoltage protect/undervoltage detect

VS5

12

I

5-V overvoltage protect/undervoltage detect

DETAILED DESCRIPTION

Power-Good and Power-Good Delay

A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer

manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that

the 5-VDC and 3.3-VDC outputs are above the undervoltage threshold limit. At this time the converter should be

able to provide enough power to assure continuous operation within the specification. Conversely, when either

the 5-VDC or the 3.3-VDC output voltages fall below the undervoltage threshold, or when main power has been

removed for a sufficiently long time so that power supply operation is no longer assured, PGO should be

deasserted to a low state.

The power-good (PGO), DC enable (PSON), and the 5-V/3.3-V supply rails are shown in Figure 3.

Figure 3. Timing of PSON and PGO

Although there is no requirement to meet specific timing parameters, the following signal timings are

recommended:

2 ms

≤ t2 ≤ 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 ≤ 10 ms

Furthermore, motherboards should be designed to comply with the above recommended timing. If timings other

than these are implemented or required, this information should be clearly specified.

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