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TPS3808G18QDBVRQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS3808G18QDBVRQ1 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 25 page TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G15-Q1 TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1 www.ti.com SBVS085I – JANUARY 2007 – REVISED JUNE 2015 7.4 Thermal Information TPS3808Gxx-Q1 THERMAL METRIC(1) DBV (SOT-23) DRV (SON) UNIT 6 PINS 6 PINS RθJA Junction-to-ambient thermal resistance 180.9 178.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 117.8 95.6 °C/W RθJB Junction-to-board thermal resistance 27.8 135 °C/W ψJT Junction-to-top characterization parameter 18.9 6.3 °C/W ψJB Junction-to-board characterization parameter 27.3 136.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 7.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics 1.8 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C) (unless otherwise noted), typical values at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD Input supply range 1.8 6.5 V VDD = 3.3 V, RESET not asserted, MR, RESET, CT open 2.4 5 IDD Supply current (into VDD pin) μA VDD = 6.5 V, RESET not asserted, MR, RESET, CT open 2.7 6 1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA 0.3 VOL Low-level output voltage V 1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA 0.4 Power-up reset voltage(1) VOL (max) = 0.2 V, I RESET = 15 μA 0.8 V TPS3808G01-Q1 –2% ±1% 2% VIT ≤ 3.3 V –1.5% ±0.5% 1.5% Negative-going input VIT 3.3 V < VIT ≤ 5 V –2% ±1% 2% threshold accuracy VIT ≤ 3.3 V –1.25% ±0.5% 1.25% –40°C < TJ < 85°C 3.3 V < VIT ≤ 5 V –1.5% ±0.5% 1.5% TPS3808G01-Q1 1.5 3 VHYS Hysteresis on VIT pin –40°C < TJ < 85°C 1 2 %VIT 1 2.5 R MR MR internal pullup resistance VSENSE = VIT 70 90 k Ω TPS3808G01-Q1 –25 25 nA ISENSE Input current at SENSE pin VSENSE = 6.5 V 1.7 μA IOH RESET leakage current V RESET = 6.5 V, RESET not asserted 300 nA CT pin VIN = 0 V to VDD 5 CIN Input capacitance, any pin pF Other pins VIN = 0 V to 6.5 V 5 VIL MR logic low input 0 0.3 VDD V VIH MR logic high input 0.7 VDD VDD V (1) Power-up reset voltage is the lowest supply voltage (VDD) at which RESET becomes active (trise(VDD) ≥ 15 μs/V). Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 |
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