TPS3836

TPS3837

TPS3838

SLVS292E – JUNE 2000 – REVISED OCTOBER 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

NOMINAL SUPPLY VOLTAGE

(2)

TPS383xE18

1.8 V

1.71 V

TPS383xJ25

2.5 V

2.25 V

TPS383xH30

3.0 V

2.79 V

TPS383xL30

3.0 V

2.64 V

TPS383xK33

3.3 V

2.93 V

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Custom threshold voltages are available. Minimum order quantities apply. Contact factory for details and availability.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

TPS383xx

UNIT

(2)

7

V

–0.3 to 7

V

5

mA

–5

mA

±10

mA

±10

mA

Continuous total power dissipation

See Dissipation Ratings Table

–40 to +85

°C

–65 to +150

°C

Soldering temperature

+260

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to GND.

(3)

causing leakage current to flow into the RESET or RESET pin.

DISSIPATION RATINGS

DERATING FACTOR

PACKAGE

POWER RATING

POWER RATING

POWER RATING

DBV

437 mW

3.5 mW/°C

280 mW

227 mW

715 mW

7.1 mW/°C

395 mW

285 mW

1540 mW

15.4 mW/°C

845 mW

615 mW

(1)

The JEDEC low-K (1s) board used to derive this data was a 3in x 3in, two-layer board with 2-ounce copper traces on top of the board.

(2)

The JEDEC high-K (2s2p) board used to derive this data was a 3in x 3in, multilayer board with 1-ounce internal power and ground

planes and 2-ounce copper traces on the top and bottom of the board.

2

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