THERMAL

PAD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ILIM/SYNC

VDD

OSNS

FB

COMP

SS/SD

RT

SGND

BOOT1

HDRV

SW

BOOT2

PVDD

LDRV

PGND

PWRGD

PWP PACKAGE

(TOP VIEW)

TPS40021-EP

www.ti.com

SLUSB58 – SEPTEMBER 2012

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NO.

I/O

DESCRIPTION

NAME

PWP

This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high

BOOT1

16

I

side FET to be driven above the input supply rail. Connect a capacitor from this pin to the SW pin.

This pin provides a secondary bootstrapping necessary for generation of PVDD. Connect a

BOOT2

13

I

capacitor from this pin to SW.

COMP

5

O

Output of the error amplifier. Refer to Electrical Characteristics table for loading constraints.

FB

4

I

of 690 mV.

The gate drive output for the high side N-channel MOSFET switch is bootstrapped to near PVDD for

HDRV

15

O

good enhancement of the high-side switch. The HDRV switches from BOOT1 to SW.

The current limit pin is used to set the current limit threshold. A current sink from this pin to GND

sets the threshold voltage for output short circuit current across a resistor connected to VDD.

ILIM/SYNC

1

I

Synchronization is accomplished by pulling IMAX to less than 1 V for a period greater than the

minimum pulse width and then releasing. An open collector or drain device should be used. These

pulses must be of higher frequency than the free running frequency of the local oscillator.

Gate drive output for the low-side synchronous rectifier N-channel MOSFET. LDRV switches from

LDRV

11

O

PVDD to PGND.

The output sense pin is connected to a resistor divider from VOUT to GND (identical to the main

OSNS

3

O

feedback loop) and is used to sense power good condition and provides reference for the transient

comparators.

PGND

10

O

Power (high-current) ground used by LDRV.

PWRGD

9

-

Power good. This is an open-drain output which connects to the supply via an external resistor.

This pin is the regulated output of the charge-pump and provides the supply voltage for the LDRV

PVDD

12

O

driver stage. PVDD also drives the bootstrap circuit which generates the voltage on BOOT1.

External pin for programming the oscillator frequency. Connnected a resistor between this pin and

RT

7

I

GND.

SGND

8

-

Signal ground

The soft-start/shutdown pin provides user programmable soft-start timing and shutdown capability

SS/SD

6

I

for the controller.

This pin, used for overcurrent, zero-current, and in the anti-cross conduction sensing is connected

to the switched node on the converter. Output short circuit is detected by sensing the voltage at this

SW

14

I

pin with respect to VDD while the high-side switch is on. Zero current is detected by sensing the pin

voltage with respect to ground when the low-side rectifier MOSFET is on.

VDD

2

I

Power input for the device. Maximum voltage is 5.5 V. De-coupling of this pin is required.

A.

For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.

B.

PowerPAD heat slug must be connected to SGND (Pin 8), or electrically isolated from all other pins.

Copyright © 2012, Texas Instruments Incorporated

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