TPS40020

TPS40021

SLUS535D − MARCH 2003 − REVISED JULY 2007

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APPLICATION INFORMATION

The TPS4002x series of devices are low-input voltage, synchronous, voltage mode-buck controllers. A typical

application circuit is shown in Figure 1. These controllers are designed to allow construction of

high-performance dc-to-dc converters with input voltages from 2.25 V to 5.5 V, and output voltages as low as

690 mV. Using a top side N-channel MOSFET for the primary buck switch results in lower switch resistance

for a given gate charge.

The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch

turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The

reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can

be used, or that heat sinking can be reduced or even eliminated.

The TPS40021 is the controller of choice for most general purpose synchronous buck designs, operating in two

quadrant mode (i.e. source or sink current) full time. This choice provides the best performance for output

voltage load transient response over the widest load current range.

The TPS40020 operates in single quadrant mode (source current only) full time, allowing the paralleling of

converters. Single quadrant operation ensures one converter does pull current from a paralleled converter. A

converter using one of these controllers emulates a non-synchronous buck converter at light loads. When

current in the output inductor attempts to reverse, an internal zero-current detection circuit turns OFF the

synchronous rectifier and causes the current flow in the inductor to become discontinuous. At average load

currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as

a synchronous buck converter to maximize efficiency.

The controller provides for a coarse short circuit current-limit function that provides pulse-by-pulse current

limiting, as well as integrates short circuit current pulses to determine the existence of a persistant fault state

at the converter output. If a fault is detected, the converter shuts down for a period of time (determined by six

soft-start cycles) and then restarts. The current-limit threshold is adjustable with a single resistor connected

from VDD to the ILIM/SYNC pin. This overcurrent function is designed to protect against catastrophic faults

only, and cannot be guaranteed to protect against all overcurrent conditions.

The controller implements a closed-loop soft start function. Startup ramp time is set by a single external

capacitor connected to the SS/SD pin. The SS/SD pin also doubles as a shutdown function.

VOLTAGE REFERENCE

The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.69-V output, allowing output

voltages as low as 690 mV to be obtained.

Oscillator

The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of

0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors

to charge during every cycle.

Not Recommended for New Designs