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TPS4009 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS4009 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 46 page SS COMP FB RC 8 5 7 6 1 4 2 3 ISNS GDRV GND VDD 1 2 3 4 SS COMP FB RC 8 7 6 5 ISNS GDRV GND VDD TPS40200 www.ti.com SLUS659G – FEBRUARY 2006 – REVISED NOVEMBER 2014 5 Pin Configuration and Functions 8 PINS 8 PINS VSON (DRB) PACKAGE SOIC (D) PACKAGE (BOTTOM VIEW) (TOP VIEW) Pin Functions PIN I/O DESCRIPTION NAME NO. COMP 3 O Error amplifier output. Connect control loop compensation network from COMP to FB. FB 4 I Error amplifier inverting input. Connect feedback resistor network center tap to this pin. GND 5 Device ground. GDRV 6 O Driver output for external P-channel MOSFET Current-sense comparator input. Connect a current sense resistor between ISNS and VDD in order to set ISNS 7 I desired overcurrent threshold. Switching frequency setting RC network. Connect a capacitor from the RC pin to the GND pin and connect a resistor from the VDD pin to the RC pin. The device may be synchronized to an external clock by connecting RC 1 I an open drain output to this pin and pulling it to GND. For mor info on pulse width for synchronization, please refer to the Synchronizing the Oscillator section. Soft-start programming pin. Connect capacitor from SS to GND to program soft start time. Pulling this pin SS 2 I below 150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also functions as a restart timer for overcurrent events. VDD 8 I System input voltage. Connect local bypass capacitor from VDD to GND. Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS40200 |
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