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TPS43330QDAPRQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS43330QDAPRQ1 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 48 page  TPS43330-Q1, TPS43332-Q1 www.ti.com SLVSA82F – MARCH 2011 – REVISED DECEMBER 2014 Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. SA1 10 I High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle SA2 11 I and VIN. (SA1 positive node, SA2 negative node). SB1 29 I High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle SB2 28 I and VIN. (SB1 positive node, SB2 negative node). Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate SSA 14 O capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a tracking input to this pin. Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of 0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate SSB 25 O capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a tracking input to this pin. If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock, this overriding the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits SYNC 20 I transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads. On the TPS43332-Q1 device, a high level enables frequency-hopping spread spectrum, whereas an open or a low level disables it. Battery input sense for the boost controller. If, with the boost controller enabled, the voltage at VBAT falls below VBAT 1 I the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed boost output voltage. Main Input pin. This is the buck-controller input pin as well as the output of the boost regulator. Additionally, VIN VIN 38 I powers the internal control circuits of the device. The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck VREG 35 O and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtains its power from either VIN or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS43330-Q1 TPS43332-Q1 |
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