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STK11C68-5L55M Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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4 / 10 page STK11C68-M 4-34 #1 #2 Alt. MIN MAX MIN MAX MIN MAX SYMBOLS STK11C68-35M STK11C68-45M STK11C68-55M NO. PARAMETER UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX NO. PARAMETER UNITS WRITE CYCLES #1 & #2; G low SYMBOLS STK11C68-35M STK11C68-45M STK11C68-55M 12 tAVAV tAVAV tWC Write Cycle Time 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 30 35 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 30 35 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 18 20 30 ns 16 t WHDX t EHDX t DH Data Hold After End of Write 0 0 0 ns 17 t AVWH t AVEH t AW Address Set-up to End of Write 30 35 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns WRITE CYCLES #1 & #2; G high (VCC = 5.0V ± 10%) 12 t AVAV t AVAV t WC Write Cycle Time 45 45 55 ns 13 t WLWH t WLEH t WP Write Pulse Width 35 35 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 35 35 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 30 30 30 ns 16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 35 35 45 ns 18 t AVWL t AVEL t AS Address Set-up to Start of Write 0 0 0 ns 19 t WHAX t EHAX t WR Address Hold After End of Write 0 0 0 ns 20 tWLQZ i,m tWZ Write Enable to Output Disable 35 35 35 ns 21 tWHQX tOW Output Active After End of Write 5 5 5 ns Note i: Measured + 200mV from steady state output voltage. Note k: E or W must be ≥ V IH during address transitions. Note m: If W is low when E goes low, the outputs remain in the high impedance state. (VCC = 5.0V ± 10%) |
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