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TPS53632 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS53632 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 43 page TPS53632 SLUSBW8 – SEPTEMBER 2014 www.ti.com Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. Voltage divider to VREF. A resistor to GND sets the ramp setting voltage. The RAMP setting can be RAMP 11 I used to override the factory ramp setting. SCL 31 I Serial digital clock line. SDA 1 I/O Serial digital I/O line. When high, the driver enters FCCM mode; otherwise, the driver is in DCM mode. Driving the tri-state SKIP 7 O level on this pin puts the drivers into a low power sleep mode. The voltage sets the 3 LSBs of the I2C address. The resistance to GND selects 1 of 8 slew rates. The SLEWA 15 I start-up slew rate (EN transitions high) is SLEWRATE/2. The ADDRESS and SLEWRATE values are latched at start-up. VINTF 14 I Input voltage to interface logic. Voltage level can be between 1.62 V and 3.5 V. 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with V5A 28 I ceramic capacitor with a value of at least 1 µF. 10-k Ω resistor to the VIN pin provides input voltage information to the on-time circuits for both VIN 16 I converters. VDD 2 I 3.3-V digital power input. Bypass this pin to GND with a capacitor with a value of at least 1 µF. Voltage sense line. Tie directly to VOUT sense point of processor. Tie to VOUT on PCB with a 10-Ω VFB 24 I resistor to provide feedback when the microprocessor is not populated. The resistance between VFB and GFB is > 1 M Ω VREF 27 O 1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor. PAD GND – Thermal pad Tie to the ground plane with multiple vias. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT PWM3, PWM2, PWM1, SKIP, V5A –0.3 6.0 VIN –0.3 30.0 COMP, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3, DROOP, EN, Input voltage V FREQ-P, IMON, OCP-I, O-USR, RAMP, SCL, SDA, SLEWA, VDD, –0.3 3.6 VFB, VINTF, VREF GFB –0.2 0.2 Output voltage PGOOD –0.3 3.6 V Operating junction temperature, TJ –40 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature –55 150 °C Human body model (HBM) ESD stress voltage(1) –2 2 kV V(ESD) (1) Charged device model (CDM) ESD stress voltage(2) –750 750 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: TPS53632 |
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