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TPS53632G

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SLUSCJ3A – APRIL 2016 – REVISED JUNE 2016

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Copyright © 2016, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Current Sensing

The TPS53632G device provides independent channels of current feedback for secondary side current

doublers . These independent channels increase the system accuracy and reduce the dependence of circuit

performance on layout compared to an externally summed architecture. The design can use inductor DCR

sensing to yield the best efficiency or resistor current sensing to yield the most accuracy across wide

temperature ranges. DCR sensing can be optimized by using a NTC thermistor to reduce the variation of current

sense with temperature.

The pins CSP1, CSN1, CSP2 and CSN2 are the current sensing pins.

7.3.2

Load Transients

When the load increases suddenly, the output voltage immediately drops. This voltage drop is reflected as a

rising voltage on the DROOP pin. This rising voltage forces the PWM to pulse sooner and more frequently which

causes the inductor current to rapidly increase. As the inductor current reaches the new load current, a steady-

state operating condition is reached and the PWM switching resumes the steady-state frequency. Similarly, when

the load releases suddenly, the output voltage rises. This rise is reflected as a falling voltage on the COMP pin.

This rising voltage forces a delay in the PWM pulses until the inductor current reaches the new load current,

when the switching resumes and steady-state switching continues.

7.3.3 PWM and SKIP Signals

The PWM and SKIP signals are outputs of the controller and serve as input to the driver or DrMOS type devices.

Both are 5-V logic signals. The PWM signals are logic high when the high-side driver turns ON. The PWM signal

must be low for the low-side drive to turn ON. When both the drive signals are OFF, the PWM is in tri-state.

7.3.4 5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)

The TPS53632G device continuously monitors the voltage on the V5A, VDD and VINTF pins to ensure a value

high enough to bias the device properly and provide sufficient gate drive potential to maintain high efficiency. The

converter starts with a voltage of approximately 4.4 V and has a nominal 200 mV of hysteresis. After the 5VA,

the device.

7.3.5 Output Undervoltage Protection (UVP)

Output undervoltage protection works in conjunction with the current protection described in the Overcurrent

Protection (OCP) section. If the output voltage drops below the low PGOOD voltage threshold, then the drivers

are turned OFF until the EN pin power is cycled.

7.3.6 Overcurrent Protection (OCP)

The TPS53632G device uses a valley current limiting scheme, so the ripple current must be considered. The DC

phase-by-phase and pulse-by-pulse basis. If the voltage between the CSPx and CSNx pins is above the OCP

value, the converter delays the next ON pulse until that voltage difference drops below the OCP limit. For

inductor current sensing circuits, the voltage between the CSPx and CSNx pins is the inductor DCR value

multiplied by the resistor divider which is part of the NTC compensation network. As a result, a wide range of

OCP values can be obtained by changing the resistor divider value. In general, use the highest OCP setting

possible with the least attenuation in the resistor divider to provide as much signal to the device as possible. This

provides the best performance for all parameters related to current feedback.

In OCP mode, the voltage drops until the UVP limit is reached. Then the converter sets the PGOOD to inactive,

and the drivers are turned OFF. The converter remains in this state until the device is reset by the V5A, VDD or

VINTF rails.