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TPS54073PWPRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS54073PWPRG4 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 25 page  APPLICATION INFORMATION PCB LAYOUT AGND BOOT VSENSE COMP PWRGD PH PH PH PH PH PH PH PH PH RT SYNC SS/ENA VBIAS VIN PVIN PVIN PVIN PVIN PGND PGND PGND PGND PGND VOUT PH PVIN TOPSIDEGROUND AREA VIA toGroundPlane ANALOGGROUND TRACE EXPOSED POWERPAD AREA COMPENSATION NETWORK OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR BOOT CAPACITOR INPUT BYPASS CAPACITOR INPUT BULK FILTER FREQUENCY SET RESISTOR SLOWSTART CAPACITOR BIASCAPACITOR INPUT BYPASS CAPACITOR VIN OPTIONAL PRE-CHARGEDIODES CONNECT TOPRE-CHARGE VOLTAGESOURCE TPS54073 SLVS547 – FEBRUARY 2005 ............................................................................................................................................................................................ www.ti.com Figure 10. TPS54073 Layout The PVIN pins are connected together on the printed- additional vias at the ground side of the input and circuit board (PCB) and bypassed with a low ESR output filter capacitors. The AGND and PGND pins ceramic bypass capacitor. Care should be taken to are tied to the PCB ground by connecting them to the minimize the loop area formed by the bypass ground area under the device as shown in Figure 10. capacitor connections, the PVIN pins, and the Use a separate wide trace for the analog ground TPS54073 ground pins. The minimum recommended signal path. This analog ground is used for the bypass capacitance is a 10- µF ceramic capacitor with voltage set point divider, timing resistor RT, slow-start a X5R or X7R dielectric. The optimum placement is capacitor, and bias capacitor grounds. The PH pins as close as possible to the PVIN pins, the AGND, are tied together and routed to the output inductor. and PGND pins. See Figure 10 for an example of a Because the PH connection is the switching node, an board layout. If the VIN is connected to a separate inductor is located close to the PH pins, and the area source supply, it is bypassed with its own capacitor. of the PCB conductor is minimized to prevent There is an area of ground on the top layer of the excessive capacitive coupling. Connect the boot PCB, directly under the IC, with an exposed area for capacitor between the phase node and the BOOT pin connection to the PowerPAD. Use vias to connect as shown in Figure 10. Keep the boot capacitor close this ground area to any internal ground planes. Use to the IC, and minimize the conductor trace lengths. 8 Submit Documentation Feedback Copyright © 2005, Texas Instruments Incorporated Product Folder Link(s): TPS54073 |
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