USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Document #: 38-03032 Rev. *A
Page 6 of 12
Switching Characteristics Over the Operating Range [12]
Parameter
Description
7C371i
−143
7C371i
−110
7C371i
−83
7C371iL
−83
7C371i
−66
7C371iL
−66
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
8.5
10
12
15
ns
tPDL
Input to Output Through Transparent Input or
Output Latch[1]
11.5
13
18
22
ns
tPDLL
Input to Output Through Transparent Input
and Output Latches[1]
13.5
15
20
24
ns
tEA
Input to Output Enable[1]
13
14
19
24
ns
tER
Input to Output Disable
13
14
19
24
ns
Input Registered/Latched Mode Parameters
tWL
Clock or Latch Enable Input LOW Time[8]
2.5
3
4
5
ns
tWH
Clock or Latch Enable Input HIGH Time[8]
2.5
3
4
5
ns
tIS
Input Register or Latch Set-up Time
2
2
3
4
ns
tIH
Input Register or Latch Hold Time
2
2
3
4
ns
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
12
14
19
24
ns
tICOL
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch[1]
14
16
21
26
ns
Output Registered/Latched Mode Parameters
tCO
Clock or Latch Enable to Output[1]
66.5
8
10
ns
tS
Set-up Time from Input to Clock or Latch
Enable
56
8
10
ns
tH
Register or Latch Data Hold Time
0
0
0
0
ns
tCO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1]
12
14
19
24
ns
tSCS
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
7
9
12
15
ns
tSL
Set-up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
910
12
15
ns
tHL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
00
0
0
ns
fMAX1
Maximum Frequency with Internal Feedback
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO)
[8]
143
111
83.3
66.6
MHz
fMAX2
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL
+tWH), 1/(tS + tH), or 1/tCO)
[8]
166.7
153.8
100
83.3
MHz
fMAX3
Maximum Frequency with external feedback
(Lesser of 1/(tCO + tS) and 1/(tWL + tWH))
[8]
91
80
50
41.6
MHz
tOH-tIH
37x
Output Data Stable from Output clock minus
Input Register Hold Time for 7C37x[8,13]
00
0
0
ns
Pipelined Mode Parameters
tICS
Input Register Clock to Output Register Clock
7
9
12
15
ns
fMAX4
Maximum Frequency in Pipelined Mode
(Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH),
1/(tIS + tIH), or 1/tSCS)
125
111
76.9
62.5
MHz
Notes:
12. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
