CY2907
Single-PLL General-Purpose
EPROM Programmable Clock Generator
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07137 Rev. **
Revised September 26, 2001
CyClocks is a trademark of Cypress Semiconductor Corporation.
Features
Benefits
Single phase-locked loop architecture
Generates a custom frequency from an external source
EPROM programmability
Easy customization and fast turnaround
Factory-programmable (CY2907, CY2907I) or field-pro-
grammable (CY2907F & CY2907FI) device options
Programming support available for all opportunities
Up to two configurable outputs
Provides clocking requirements from a single device
Low-skew, low-jitter, high-accuracy outputs
Meets critical industry standard timing requirements
Power management (Power-Down, OE)
Supports low-power applications
Frequency select option
Up to 16 user-selectable frequencies
Configurable 5V or 3.3V operation
Supports industry-standard design platforms
8-pin or 14-pin SOIC packages
Industry-standard packaging saves on board space
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2907
2
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–130 MHz (5V)
500 kHz–100 MHz (3.3V)
Factory Programmable
Commercial Temperature
CY2907I
2
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
Factory Programmable
Industrial Temperature
CY2907F8
CY2907F14
210 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
Field Programmable
Commercial Temperature
CY2907F8I
CY2907F14I
210 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–90 MHz (5V)
500 kHz–66.66 MHz (3.3V)
Field Programmable
Industrial Temperature
XTALOUT
XTALIN
REFCLK
OSC.
1
2
3
4
5
6
7
10
9
8
11
14
13
12
Top View
S1
S2
S3
VSS
VSS
PD
XTALIN
S0
REFCLK
VDD
CLKA
OEA
OER
XTALOUT
CLKA
PLL
EPROM
Table
S0
S1
14-Pin SOIC
S2
S3
OER
Output
Multiplexer
and
Dividers
PD
1
2
3
4
5
8
7
6
S0
VSS
XTALIN
XTALOUT
REFCLK
VDD
CLKA
S1
8-Pin SOIC
Configuration
EPROM
and Test Logic
OEA
Logic Block Diagram
Pin Configurations