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TPS54352PWPG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS54352PWPG4 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 37 page  TPS54352,TPS54353 TPS54354,TPS54355 TPS54356,TPS54357 SLVS519A − MAY 2004 − REVISED OCTOBER 2004 www.ti.com 5 ELECTRICAL CHARACTERISTICS (CONTINUED) TJ = –40°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FALLING EDGE TRIGGERED BIDIRECTIONAL SYNC SYSTEM (SYNC PIN) SYNC out low-to-high rise time (10%/90%) (1) 25 pF to ground 200 500 ns SYNC out high-to-low fall time (90%/10%) (1) 25 pF to ground 5 10 ns Falling edge delay time (1) Delay from rising edge to rising edge of PH pins, see Figure 19 180 ° Minimum input pulse width (1) RT = 100 k Ω 100 ns Delay (falling edge SYNC to rising edge PH) (1) RT = 100 k Ω 360 ns SYNC out high level voltage 50-k Ω Resistor to ground, no pullup resistor 2.5 V SYNC out low level voltage 0.6 V SYNC in low level threshold 0.8 V SYNC in high level threshold 2.3 V SYNC in frequency range (1) Percentage of programmed frequency −10% 10% SYNC in frequency range (1) 225 770 kHz FEED− FORWARD MODULATOR (INTERNAL SIGNAL) Modulator gain VIN = 12 V, TJ = 25°C 8 V/V Modulator gain variation −25% 25% Minimum controllable ON time (1) 180 ns Maximum duty factor (1) VIN = 4.5 V 80% 86% VSENSE PIN Input bias current, VSENSE pin 1 µA ENABLE (ENA PIN) Disable low level input voltage 0.5 V TPS54352 fs = 250 kHz, RT = ground (1) 3.20 TPS54352 fs = 500 kHz, RT = Hi−Z (1) 1.60 TPS54353 fs = 250 kHz, RT = ground (1) 4.00 TPS54353 fs = 500 kHz, RT = Hi−Z (1) 2.00 TPS54354 fs = 250 kHz, RT = ground (1) 4.60 Internal slow-start time TPS54354 fs = 500 kHz, RT = Hi−Z (1) 2.30 ms Internal slow-start time (10% to 90%) TPS54355 fs = 250 kHz, RT = ground (1) 4.40 ms (10% to 90%) TPS54355 fs = 500 kHz, RT = Hi−Z (1) 2.20 TPS54356 fs = 250 kHz, RT = ground (1) 5.90 TPS54356 fs = 500 kHz, RT = Hi−Z (1) 2.90 TPS54357 fs = 250 kHz, RT = ground (1) 5.40 TPS54357 fs = 500 kHz, RT = Hi−Z (1) 2.70 Pullup current source 1.8 5 10 µA Pulldown MOSFET II(ENA)= 1 mA 0.1 V POWER GOOD (PWRGD PIN) Power good threshold Rising voltage 97% Rising edge delay (1) fs = 250 kHz 4 ms Rising edge delay (1) fs = 500 kHz 2 ms Output saturation voltage Isink = 1 mA, VIN > 4.5 V 0.05 V PWRGD Output saturation voltage Isink = 100 µA, VIN = 0 V 0.76 V PWRGD Open drain leakage current Voltage on PWRGD = 6 V 3 µA (1) Ensured by design, not production tested. |
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