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DSP56364 Datasheet(PDF) 3 Page - Motorola, Inc |
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DSP56364 Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 162 page Overview Documentation MOTOROLA DSP56364 Advance Information 3 • JTAG port. • Very low-power CMOS design, fully static design with operating frequencies down to DC. • STOP and WAIT low-power standby modes. 1.2 On-chip Memory Configuration • 1.5Kx24 Bit Y-Data RAM. • 1Kx24 Bit X-Data RAM. • 8Kx24 Bit Program ROM. • 0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. • 0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25Kx24 Bit of Program RAM. 1.3 Off-chip memory expansion • External Memory Expansion Port with 8-bit data bus. • Off-chip expansion up to 2 x 16M x 8-bit word of Data/Program memory when using DRAM. • Off-chip expansion up to 2 x 256k x 8-bit word of Data/Program memory when using SRAM. • Simultaneous glueless interface to SRAM and DRAM. 1.4 Peripheral modules • Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmitt and 2 transmitt only, master or slave. I2S, Sony, AC97, network and other programmable protocols. Unused pins of ESAI may be used as GPIO lines. • Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words. • Four dedicated GPIO lines. 1.5 Packaging • 100-pin plastic TQFP package. 2 Documentation Table 1 lists the documents that provide a complete description of the DSP56364 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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