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CY7C4261
CY7C4271
Document #: 38-06015 Rev. *B
Page 5 of 18
Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration
FF
FF
EF
EF
WRITECLOCK (WCLK)
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAF)
FULL FLAG (FF)# 1
CY7C4261/71
9
18
DATA IN (D)
RESET (RS)
9
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
9
DATA OUT (Q)
918
Read Enable 2 (REN2)
CY7C4261/71
EMPTY FLAG (EF) #2
FULL FLAG (FF)# 2
Read Enable 2 (REN2)