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SN65HVD74DR Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVD74DR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 41 page SN65HVD70, SN65HVD71, SN65HVD73, SN65HVD74, SN65HVD76, SN65HVD77 SLLSEI9E – MAY 2014 – REVISED OCTOBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage VCC –0.5 5.5 V Voltage Range at any bus pin (A, B, Y, or Z) –13 16.5 V Input voltage Range at any logic pin (D, DE, or RE) –0.3 5.7 V Voltage input range, transient pulse, any bus pin (A, B, Y, or Z) through 100 Ω –100 100 V Output current Receiver output –24 24 mA Junction temperature, TJ 170 °C Continuous total power dissipation See the Thermal Information table (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –65 150 °C Human body model (HBM), per JEDEC specification JESD22-A114, all pins –8 8 kV Charged device model (CDM), per JEDEC specification JESD22-C101, all pins –1.5 1.5 kV Machine model (MM), all pins –300 300 V V(ESD) Electrostatic discharge IEC 61000-4-2 ESD (Air-Gap Discharge), bus pins and GND(1)(2) –12 12 kV IEC 61000-4-2 ESD (Contact Discharge), bus pins and GND –12 12 kV IEC 61000-4-4 EFT (Fast transient or burst), bus pins and GND –4 4 kV IEC 60749-26 ESD (Human Body Model), bus pins and GND(2) –30 30 kV (1) By inference from contact-discharge results, see the Application and Implementation section (2) Limited by tester capability. 7.3 Recommended Operating Conditions MIN NOM MAX UNIT VCC Supply voltage 3 3.3 3.6 V VI Input voltage at any bus pin (separately or common mode) (1) –7 12 V VIH High-level input voltage (Driver, driver enable, and receiver enable inputs) 2 VCC V VIL Low-level input voltage (Driver, driver enable, and receiver enable inputs) 0 0.8 V VID Differential input voltage –12 12 V IO Output current, Driver –60 60 mA IO Output current, Receiver –8 8 mA RL Differential load resistance 54 60 Ω CL Differential load capacitance 50 pF HVD70, HVD71 400 kbps 1/tUI Signaling rate HVD73, HVD74 20 Mbps HVD76, HVD77 50 TA (2) Operating free-air temperature (See the Application and Implementation for thermal –40 125 °C information) TJ Junction Temperature –40 150 °C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating because of internal power dissipation should be considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which disables the driver outputs when the junction temperature reaches 170°C. 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: SN65HVD70 SN65HVD71 SN65HVD73 SN65HVD74 SN65HVD76 SN65HVD77 |
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