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TPS62184YZFR Datasheet(PDF) 3 Page - Texas Instruments |
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TPS62184YZFR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 32 page A B C D E F 1 2 3 4 F E D C B A TPS62184 www.ti.com SLVSCQ5A – DECEMBER 2014 – REVISED FEBRUARY 2015 spacing 6 Pin Configuration and Functions spacing 24-Pin DSBGA YZF Package (Top View - Left, Bottom View - Right) Pin Functions PIN(1) DESCRIPTION NAME NUMBER AGND C4 Analog Ground. Connect on PCB directly with PGND. EN E4 Enable input (High = enabled, Low = disabled) Output voltage feedback. Connect resistive voltage divider to this pin and AGND. On TPS62182, FB B4 connect to AGND. Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain PG F4 (requires pull-up resistor) A3, B3, C3, D3, PGND Common power ground. E3, F3 Soft-Start and Tracking Pin. An external capacitor connected to this pin sets the internal voltage SS/TR D4 reference rise time. Switch node for Phase 1 (master), connected to the internal MOSFET switches. Connect inductor 1 SW1 A2, B2, C2 between SW1 and output capacitor. Switch node for Phase 2 (follower), connected to the internal MOSFET switches. Connect inductor 2 SW2 D2, E2, F2 between SW2 and output capacitor. VIN1 A1, B1, C1 Supply voltage for Phase 1. VIN2 D1, E1, F1 Supply voltage for Phase 2. VO A4 Output Voltage Connection (1) For more information about connecting pins, see Detailed Description and Application Information sections. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS62184 |
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