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DS90CF363 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DS90CF363 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 9 page AC Timing Diagrams (Continued) DS90CF363 Pin Description — FPD Link Transmitter Pin Name I/O No. Description TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). TxOUT+ O 3 Positive LVDS differentiaI data output. TxOUT− O 3 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down. V CC I 4 Power supply pins for TTL inputs. GND I 4 Ground pins for TTL inputs. PLL V CC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS V CC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. Applications Information The DS90CF363 and DS90CF364 are backward compatible with the existing 5V FPD Link transmitter/receiver pair (DS90CF563 and DS90CF564). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the V CC, LVDS VCC and PLL VCC of both the transmitter and receiver devices. This change may enable the re- moval of a 5V supply from the system, and power may be supplied from an existing 3V power source. 2. The DS90CF363 transmitter input and control inputs ac- cept 3.3V TTL/CMOS levels. They are not 5V tolerant. DS100032-20 FIGURE 12. Transmitter LVDS Output Pulse Position Measurement www.national.com 7 |
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