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IDT71T75802S133PF Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT71T75802S133PF Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 25 page 6.42 4 IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Recommended Operating Temperature and Supply Voltage Pin Configuration 512K x 36 NOTES: 1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH. 2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device. Top View 100 TQFP Recommended DC Operating Conditions NOTE: 1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle. Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.375 2.5 2.625 V VDDQ I/O Supply Voltage 2.375 2.5 2.625 V VSS Ground 0 0 0 V VIH Input High Voltage - Inputs 1.7 ____ VDD +0.3 V VIH Input High Voltage - I/O 1.7 ____ VDDQ+0.3 V VIL Input Low Voltage -0.3(1) ____ 0.7 V 5313 tbl 03 Grade Ambient Temperature(1) VSS VDD VDDQ Commercial 0° C to +70° C OV 2.5V ± 5% 2.5V ± 5% Industrial -40° C to +85° C OV 2.5V ± 5% 2.5V ± 5% 5313 tbl 05 100 999897 96 9594939291 90 87868584 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O31 I/O30 VDDQ VSS I/O29 I/O28 I/O27 I/O26 VSS VDDQ I/O25 I/O24 VSS VDD I/O23 I/O22 VDDQ VSS I/O21 I/O20 I/O19 I/O18 VSS VDDQ I/O17 I/O16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VDD I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 5313 drw 02 VDD(1) I/O15 I/OP3 VDD(1) I/OP4 I/OP1 VDD(1) I/OP2 ZZ , NOTE: 1. During production testing, the case temperature equals the ambient temperature. |
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