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IDT70V27L15BFI Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT70V27L15BFI Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 22 page Commercial and Industrial Temperature Range IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM 9 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4,6) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 5. Refer to Chip Enable Truth Table. 6. Industrial temperature: for other speeds, packages and powers contact your sales office. 70V27X15 Com'l Only 70V27X20 Com'l Only 70V27X25 Com'l Only Unit Symbol Parameter Min. Max. Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 20 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tABE Byte Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 12 ____ 15 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ 3 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 12 ____ 15 ns tPU Chip Enable to Power Up Time (2,5) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2,5) ____ 15 ____ 20 ____ 25 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)10 ____ 10 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 15 ____ 20 ____ 35 ns 3603 tbl 12a 70V27X35 Com'l & Ind 70V27X55 Com'l Only Unit Symbol Parameter Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 35 ____ 55 ____ ns tAA Address Access Time ____ 35 ____ 55 ns tACE Chip Enable Access Time (3) ____ 35 ____ 55 ns tABE Byte Enable Access Time (3) ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time (1,2) ____ 20 ____ 25 ns tPU Chip Enable to Power Up Time (2,5) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2,5) ____ 45 ____ 50 ns tSOP Semaphore Flag Update Pulse ( OE or SEM)15 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 45 ____ 65 ns 3603 tbl 12b |
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