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GD25D05B Datasheet(PDF) 7 Page - ELM Electronics |
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GD25D05B Datasheet(HTML) 7 Page - ELM Electronics |
7 / 28 page 7 Rev.1.0 28 - GD25D05BxIGx Uniform sector dual and quad serial flash http://www.elm-tech.com ♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. ♦ Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI. Status Register Content Memory Content BP2 BP1 BP0 Blocks Addresses Density Portion 0 0 0 NONE NONE NONE NONE 0 0 1 Sector 0 to 29 000000H-00DFFFH 56KB Lower 14/16 0 1 0 Sector 0 to 27 000000H-00BFFFH 48KB Lower 12/16 0 1 1 Sector 0 to 23 000000H-007FFFH 32KB Lower 8/16 1 × × All 000000H-00FFFFH 64KB All Table 1. GD25D05B Protected area size 6. STATUS REGISTER The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress. When WIP bit is cleared to 0, it means the device is not in program/erase/write status register progress. The default value of WIP is 0. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no write Status Register, Program or Erase command is accepted. The default value of WEL is 0. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Statue Register (WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1). Becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed,if the Block Protect (BP2, BP1, BP0) bits are all 0.The default value of BP2:0 are 0s. SRP bit. The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the hardware Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, S7 S6 S5 S4 S3 S2 S1 S0 SRP Reserved Reserved BP2 BP1 BP0 WEL WIP |
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