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NCP1207APG Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP1207APG Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 18 page  NCP1207A, NCP1207B www.onsemi.com 8 APPLICATION INFORMATION Introduction The NCP1207A/B implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint whereas the core reset detection triggers the turn−on event. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC/DC adapters, consumer electronics, auxiliary supplies, etc. Due to its high−performance High−Voltage technology, the NCP1207A/B incorporates all the necessary components / features needed to build a rugged and reliable Switch−Mode Power Supply (SMPS): • Transformer core reset detection: borderline / critical operation is ensured whatever the operating conditions are. As a result, there are virtually no primary switch turn−on losses and no secondary diode recovery losses. The converter also stays a first−order system and accordingly eases the feedback loop design. • Quasi−resonant operation: by delaying the turn−on event, it is possible to re−start the MOSFET in the minimum of the drain−source wave, ensuring reduced EMI / video noise perturbations. In nominal power conditions, the NCP1207A/B operates in Borderline Conduction Mode (BCM) also called Critical Conduction Mode. • Dynamic Self−Supply (DSS): due to its Very High Voltage Integrated Circuit (VHVIC) technology, ON Semiconductor’s NCP1207A/B allows for a direct pin connection to the high−voltage DC rail. A dynamic current source charges up a capacitor and thus provides a fully independent VCC level to the NCP1207A/B. As a result, there is no need for an auxiliary winding whose management is always a problem in variable output voltage designs (e.g. battery chargers). • Overvoltage Protection (OVP): by sampling the plateau voltage on the demagnetization winding, the NCP1207A/B goes into latched fault condition whenever an over−voltage condition is detected. The controller stays fully latched in this position until the VCC is cycled down 4.0 V, e.g. when the user un−plugs the power supply from the mains outlet and re−plugs it. • External latch trip point: by externally forcing a level on the OVP greater than the internal setpoint, it is possible to latchoff the IC, e.g. with a signal coming from a temperature sensor. • Adjustable skip cycle level: by offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. This point guarantees a noise−free operation with cheap transformer. This option also offers the ability to fix the maximum switching frequency when entering light load conditions. • Overcurrent Protection (OCP): by continuously monitoring the FB line activity, NCP1207A/B enters burst mode as soon as the power supply undergoes an overload. The device enters a safe low power operation which prevents from any lethal thermal runaway. As soon as the default disappears, the power supply resumes operation. Unlike other controllers, overload detection is performed independently of any auxiliary winding level. In presence of a bad coupling between both power and auxiliary windings, the short circuit detection can be severely affected. The DSS naturally shields you against these troubles. Dynamic Self−Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with some simple logical equations: POWER−ON: IF VCC < VCCOFF THEN Current Source is ON, no output pulses IF VCC decreasing > VCCON THEN Current Source is OFF, output is pulsing IF VCC increasing < VCCOFF THEN Current Source is ON, output is pulsing Typical values are: VCCOFF = 12 V, VCCON = 10 V To better understand the operational principle, Figure 12’s sketch offers the necessary light. Figure 12. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor VRIPPLE = 2 V ON OFF VCCOFF = 12 V VCCON = 10 V Output Pulses |
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