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NCP1230D65R2G Datasheet(PDF) 2 Page - ON Semiconductor |
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NCP1230D65R2G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 21 page NCP1230 www.onsemi.com 2 Figure 1. Typical Application Example 1 8 2 3 4 7 6 5 CBulk HV + MC33262/33260 PFC_VCC OVP 1 8 2 3 4 7 6 5 NCP1230 OVP + GN- D Vout Rsense GND Ramp Comp 10 k VCC Cap PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Pin Description 1 PFC VCC This pin provides the bias voltage to the PFC controller. This pin is a direct connection to the VCC pin (Pin 6) via a low impedance switch. In standby and during the startup sequence, the switch is open and the PFC VCC is shut down. As soon as the aux. winding is stabilized, Pin 1 connects to the VCC pin and provides bias to the PFC controller. It goes down in standby and fault conditions. 2 FB Feedback Signal An optocoupler collector pulls this pin low to regulate. When the current setpoint reaches 25% of the maximum peak, the controller skips cycles. 3 CS/OVP Current Sense This pin incorporates three different functions: the current sense function, an internal ramp compensation signal and a 3.0 V latch−off level which latches the output off until VCC is recycled. 4 GND IC Ground − 5 DRV Driver Output With a drive capability of +500 mA / −800 mA, the NCP1230 can drive large Qg MOSFETs. 6 VCC VCC Input The controller accepts voltages up to 18 V and features a UVLO turn−off threshold of 7.7 V typical. 7 NC − − 8 HV High−Voltage This pin connects to the bulk voltage and offers a lossless startup sequence. The charging current is high enough to support the bias needs of a PWM controller through Pin 1. |
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