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TDA8359J Datasheet(PDF) 4 Page - NXP Semiconductors |
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TDA8359J Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 20 page 2002 Jan 21 4 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS TDA8359J FUNCTIONAL DESCRIPTION Vertical output stage The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. For processors with output currents, the currents are converted to voltages by the conversion resistors RCV1 and RCV2 (see Fig.5) connected to pins INA and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, providing feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input voltage and the output current is defined by: Vi(dif)(p-p) =Io(p-p) × RM Vi(dif)(p-p) = VINA − VINB The output current should not exceed 3.2 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the values of RM and the internal bondwire resistance (typical value of 50 m Ω) the actual value of the current in the deflection coil will be approximately 5% lower than calculated. Flyback supply The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew rate value of more than 300 V/ µs. Protection The output circuit contains protection circuits for: • Too high die temperature • Overvoltage of output A. Guard circuit A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions: • During thermal protection (Tj = 170 °C) • During an open-loop condition. The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller. Damping resistor compensation HF loop stability is achieved by connecting a damping resistor RD1 across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan. The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time. For that purpose a compensation resistor RCMP in series with a zener diode is connected between pins OUTA and INA (see Fig.4). The zener diode voltage value should be equal to VP. The value of RCMP is calculated by: where: • Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback • Rcoil is the deflection coil resistance • VZ is the voltage of zener diode D4. R CMP V FB V loss FB () – V Z – () R D1 × R CV1 × V FB V loss FB () – I coil peak () R coil × – () R M × ------------------------------------------------------------------------------------------------------------ = |
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