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TMS320VC5502PGF300 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320VC5502PGF300 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 189 page  www.ti.com TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 3-37 Parallel GPIO Enable Register 1 Layout (0x4403) ........................................................................... 92 3-38 Parallel GPIO Direction Register 1 Layout (0x4404) ......................................................................... 93 3-39 Parallel GPIO Data Register 1 Layout (0x4405) .............................................................................. 93 3-40 Parallel GPIO Enable Register 2 Layout (0x4406) ........................................................................... 94 3-41 Parallel GPIO Direction Register 2 Layout (0x4407) ......................................................................... 94 3-42 Parallel GPIO Data Register 2 Layout (0x4408) .............................................................................. 95 3-43 External Bus Control Register Layout (0x8800) ............................................................................... 97 3-44 XPORT Configuration Register Layout (0x0100) ............................................................................. 99 3-45 XPORT Bus Error Register Layout (0x0102) ................................................................................ 100 3-46 DPORT Configuration Register Layout (0x0200) ............................................................................ 101 3-47 DPORT Bus Error Register Layout (0x0202) ................................................................................ 101 3-48 IPORT Bus Error Register Layout (0x0302) ................................................................................. 102 3-49 System Configuration Register Layout (0x07FD) ........................................................................... 103 3-50 Time-Out Control Register Layout (0x9000) ................................................................................. 104 3-51 IFR0, IER0, DBIFR0, and DBIER0 Registers Layout ....................................................................... 122 3-52 IFR1, IER1, DBIFR1, and DBIER1 Registers Layout ....................................................................... 122 3-53 Bad TCK Transition ............................................................................................................. 123 3-54 Good TCK Transition ............................................................................................................ 124 3-55 Sample Noise Filtering Circuitry ............................................................................................... 124 5-1 3.3-V Test Load Circuit ......................................................................................................... 129 5-2 Internal System Oscillator With External Crystal ............................................................................ 130 5-3 Bypass Mode Clock Timings ................................................................................................... 132 5-4 External Multiply-by-N Clock Timings ......................................................................................... 134 5-5 ECLKIN Timings for EMIF ...................................................................................................... 135 5-6 ECLKOUT1 Timings for EMIF Module ........................................................................................ 135 5-7 ECLKOUT2 Timings for EMIF Module ........................................................................................ 135 5-8 Asynchronous Memory Read Timings ........................................................................................ 137 5-9 Asynchronous Memory Write Timings ........................................................................................ 138 5-10 Programmable Synchronous Interface Read Timings (With Read Latency = 2) ........................................ 140 5-11 Programmable Synchronous Interface Write Timings (With Write Latency = 0) ........................................ 141 5-12 Programmable Synchronous Interface Write Timings (With Write Latency = 1) ........................................ 141 5-13 SDRAM Read Command (CAS Latency 3) .................................................................................. 143 5-14 SDRAM Write Command ....................................................................................................... 143 5-15 SDRAM ACTV Command ...................................................................................................... 144 5-16 SDRAM DCAB Command ...................................................................................................... 144 5-17 SDRAM DEAC Command ...................................................................................................... 145 5-18 SDRAM REFR Command ...................................................................................................... 145 5-19 SDRAM MRS Command ....................................................................................................... 146 5-20 SDRAM Self-Refresh Timings ................................................................................................. 146 5-21 EMIF.HOLD/HOLDA Timings .................................................................................................. 147 5-22 Reset Timings .................................................................................................................... 149 8 List of Figures |
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