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U5021M-NFP Datasheet(PDF) 4 Page - ATMEL Corporation |
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U5021M-NFP Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 11 page 4 U5021M 4756C–AUTO–09/04 Figure 3. Period t versus R 1, at C1 = 500 pF Figure 4. Power-on Reset and Switch-over Mode Supply Voltage Monitoring, Pin 5 During ramp-up of the supply voltage and in the case of supply-voltage drops the inte- grated power-on reset (POR) circuitry sets the internal logic to a defined basic status and generates a reset pulse at the reset output, pin 5. A hysteresis in the POR threshold prevents the circuit from oscillating. During ramp-up of the supply voltage, the reset out- put stays active for a specified period of time (t 0) in order to bring the microcontroller into its defined reset status (see Figure 4). Pin 5 has an open-drain output. Switch-over Mode Time, Pin 3 The switch-over mode time enables the synchronous operation of microcontroller and watchdog. When the power-on reset time has elapsed, the watchdog has to be switched to monitoring mode by the microcontroller by a “low” signal transmitted to the mode pin (pin 3) within the time-out period, t1. If the low signal does not occur within t1 (see Figure 4), the watchdog generates a reset pulse, t6, and t1 starts again. Microcontroller and watchdog are synchronized with the switch-over mode time, t1, each time a reset pulse is generated. 1.00 10.00 100.00 1000.00 1 10 100 1000 t (µs) C 1 = 500 pF 4.5 V 5.5 V 5.0 V R 1 (kΩ) t 0 Reset Out Mode VDD Pin 6 Pin 5 Pin 3 t 1 t 6 |
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