Data Sheet S14920EJ3V0DS

5

CONTENTS

1. PIN FUNCTIONS..................................................................................................................................... 7

1.1 Cable Interface Pins ........................................................................................................................ 7

1.2 Link Interface Pins........................................................................................................................... 7

1.3 Control Pins ..................................................................................................................................... 8

1.4 IC ....................................................................................................................................................... 8

1.5 Power Supply Pins .......................................................................................................................... 8

1.6 Other Pins ........................................................................................................................................ 8

2. PHY REGISTERS..................................................................................................................................... 9

2.1 Complete Structure for PHY Registers.......................................................................................... 9

2.2 Port Status Page (Page 000)......................................................................................................... 12

2.3 Vendor ID Page (Page 001) ........................................................................................................... 13

2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 13

3. INTERNAL FUNCTION .......................................................................................................................... 14

3.1 Link Interface ................................................................................................................................. 14

3.1.1 Connection Method............................................................................................................................... 14

3.1.2 LPS (Link Power Status)....................................................................................................................... 14

3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins .................................................................................................... 14

3.1.4 SCLK..................................................................................................................................................... 14

3.1.5 LKON .................................................................................................................................................... 15

3.1.6 DIRECT................................................................................................................................................. 15

3.1.7 Isolation Barrier..................................................................................................................................... 15

3.2 Cable Interface............................................................................................................................... 17

3.2.1 Connections .......................................................................................................................................... 17

3.2.2 Cable Interface Circuit .......................................................................................................................... 18

3.2.3 Unused Ports ........................................................................................................................................ 18

3.2.4 CPS....................................................................................................................................................... 18

3.3 Suspend/Resume .......................................................................................................................... 18

3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 18

3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 18

3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 19

3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 19

3.4.2 PLL........................................................................................................................................................ 19

3.5 CMC ................................................................................................................................................ 19

3.6 PC0-PC2 ......................................................................................................................................... 19

3.7 RESETB .......................................................................................................................................... 19

3.8 RI1 ................................................................................................................................................... 19

4. PHY/LINK INTERFACE ......................................................................................................................... 20

4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface ............................................ 20

4.2 Link-on Indication.......................................................................................................................... 21

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)....................................................... 22

4.3.1 CTL0, CTL1 .......................................................................................................................................... 22

4.3.2 LREQ .................................................................................................................................................... 22

4.3.3 SCLK Timing......................................................................................................................................... 26