UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

1



FEATURES

Access time : 35/70ns (max.)

Low power consumption :

Operating : 45/30 mA (typ.)

CMOS Standby : 2mA (typ.) normal

2

µA (typ.) L-version

1

µA (typ.) LL-version

Single 4.5V~5.5V power supply

Operating temperature :

Commercial : 0℃~70℃

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 2V (min.)

Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

FUNCTIONAL BLOCK DIAGRAM

DECODER

I/O DATA

CIRCUIT

CONTROL

CIRCUIT

8K × 8

MEMORY

ARRAY

COLUMN I/O

OE

WE

A0-A12

Vcc

Vss

I/O1-I/O8

CE1

CE2

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A12

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

1

CE ,CE2

Chip Enable Inputs

WE

Write Enable Input

OE

Output Enable Input

Power Supply

Ground

NC

No connection

GENERAL DESCRIPTION

The UT6264C is a 65,536-bit low power CMOS

static random access memory organized as 8,192

words by 8 bits. It is fabricated using high

performance, high reliability CMOS technology.

Easy memory expansion is provided by using two

chip enable input.(

1

CE ,CE2) ,and supports low

data

retention

voltage for

battery back-up

operation with low data retention current.

The UT6264C operates from a single 4.5V~5.5V

power supply and all inputs and outputs are fully

TTL compatible.

PIN CONFIGURATION

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

Vcc

A8

A9

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

PDIP/SOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

1

CE

WE

OE

CE2

NC