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CS5451A Datasheet(PDF) 11 Page - Cirrus Logic |
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CS5451A Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 14 page CS5451A DS635PP1 11 interface (after each A/D conversion cycle). Note: SCLK is not active during FSO high. For 96 SCLK periods after FSO falls, SCLK is ac- tive and SDO produces valid output. Six channels of 16 bit data are output, MSB first. Voltage and current measurements are output (in that order) for three phases. SCLK will then be held low until the next sample period. 3.5 System Initialization When power to the CS5451A is applied, the chip must be held in a reset condition using the RESET input. A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns. 3.6 Analog Inputs The analog inputs of the CS5451A are bipolar volt- age inputs: Three voltage channel inputs VIN(1-3) and three current channel inputs IIN(1-3). The CS5451A accommodates a full scale range of 80 mVP-P or 1. 6VP-P on the Current Channels and 1.6 VP-P on the Voltage Channels. 3.7 Voltage Reference The CS5451A is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference SCLK FSO SDO Channel 1 V Channel 2 I Channel 3 I Channel 2 V Channel 3 V Channel 1 I Each data segment is 16 bits long. 96 SCLKs Figure 3. Serial Port Data Transfer SCLK FSO SDO 12 15 14 13 0 1 2 3 4 5 6 7 8 9 10 11 15 14 13 12 11 10 9 8 7 65 4 321 Channel 1 ( I ) Channel 1 ( V ) 01 5 1 4 . . . Ch. 2 ( V ) Ch. 2 ( I ) Ch. 3 ( V ) Ch. 3 ( I ) ... ... ... . . . . . . . . . [ Undefined ] [ Undefined ] . . . . . . . . . 0 1 2 3 96 SCLKs Figure 4. Close-up of One Data Frame |
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