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CY7C1354B
CY7C1356B
Document #: 38-05114 Rev. *C
Page 9 of 29
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE ZZ
ADV/LD
WE BWx
OE
CEN CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Three-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Three-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy
Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Three-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Three-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE
ABORT
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Three-State
WRITE ABORT
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Three-State
IGNORE
CLOCK EDGE
(Stall)
Current
X
L
X
X
X
X
H
L-H
-
Sleep MODE
None
X
H
X
X
X
X
X
X
Three-State
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[a:d] = Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active.
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