USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C343
Document #: 38-03015 Rev. *B
Page 3 of 19
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array config-
uration, simplifies design by ensuring that internal signal
skews or races are avoided. The result is simpler design imple-
mentation, often in a single pass, without the multiple internal
logic placement and routing iterations required for a program-
mable gate array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C343 may be easily determined
using Warp®, Warp Professional™, or Warp Enterprise™
software. The CY7C343 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C343 contains circuitry to protect
device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2
µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND, directly
at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from a straight input pin.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. tS2 should be used if data is applied at
an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting
frequency in the data path mode unless 1/(tWH + tWL) is less
than 1/tS2.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tS1. Determine which
of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins. If any data is
applied to an I/O pin, tAS2 must be used as the required set-up
time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH)
becomes the limiting frequency in the data path mode unless
1/(tAWH + tAH) is less than 1/(tAS2 + tAH).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous configu-
ration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
The parameter tAOH indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same clock as the CY7C343.
In general, if tAOH is greater than the minimum required input
hold
time
of
the
subsequent
logic
(synchronous
or
asynchronous), then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same. This
also applies if expander logic is used in the clock signal path
of the driving device, but not for the driven device. This is due
to the expander logic in the second device’s clock signal path
adding an additional delay (tEXP), causing the output data from
the preceding device to change prior to the arrival of the clock
signal at the following device’s register.
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