CY7C64613
Document #: 38-08005 Rev. *B
Page 7 of 42
must be free running. The FIFOs can be controlled either synchronously (using strobe signals and a clock) or asynchronously
(using strobe signals only). The slave FIFO data is available as two 8-bit buses, which may be used simultaneously to operate
as a single 16-bit data bus. The 16-bit connection, along with fast double-byte mode, combine to give fast conversion between
8- and 16-bit buses. A flexible set of FIFO flags (full, empty, and programmable) provide FIFO flow control.
2.5
DMA
With many sources and destinations for USB data, such as endpoint buffers, slave FIFOs, and internal/external RAM buffers, it
is important to move blocks of data between them quickly. Using internal DMA, the 8051 sets up source, destination, and transfer
length registers, and then initiates a DMA transfer. The maximum DMA transfer rate occurs between internal resources, such as
endpoint buffers and slave FIFOs. This maximum rate is one byte per 48-MHz clock, or 48 Mbytes per second.
2.6
Flexible Configuration
The EZ-USB FX supports a highly configurable I/O structure. Figure 2-1 on page 8 shows the general scheme of the assignment
of pins to I/O ports. The 80- and 56-pin products are subsets of the 128-pin products, hence they follow a similar scheme. For
details of how to set the configuration registers to configure the I/O ports, consult “CY7C64613 Pin Descriptions” on page 14 of
this data sheet and the EZ-USB FX TRM.
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