Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06010 Rev. *A
Revised August 22, 2003
Features
• High-speed, low-power, first-in, first-out (FIFO)
memories
• 64 x 9 (CY7C4421V)
• 256 x 9 (CY7C4201V)
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
• High-speed 66-MHz operation (15-ns read/write cycle
time)
• Low power (ICC = 20 mA)
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V-tolerant inputs VIH max= 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Width expansion capability
• Space saving 32-pin 7 mm × 7 mm TQFP
• 32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
Pin Configuration
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
− 8
RCLK
EF
PAE
PAF
Q0
− 8
WEN1
WCLK
RS
OE
Dual Port
RAM Array
64 x 9
8Kx 9
WEN2/LD
REN1 REN2
FF
PLCC
D1
D0
RCLK
VCC
GND
WCLK
WEN2/LD
Q8
Q7
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
REN1
OE
REN2
43 21
3130
32
D1
D0
RCLK
GND
PAF
PAE
REN1
REN2
21
22
23
24
27
28
29
25
26
141516 171819 20
17
18
19
20
21
22
23
24
14 15 16
910 11 12 13
31 30
32
29 28 27
25
26
Q6
Q5
WEN1
RS
VCC
WCLK
WEN2/LD
Q8
Q7
Q6
Q5
WEN1
TQFP
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