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HT46C64 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT46C64 Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 47 page  HT46R64/HT46C64 Rev. 1.40 11 September 21, 2004 Once an interrupt subroutine is serviced, other inter- rupts except NMI are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nest- ing. Other interrupt requests may take place during this interval, but only the interrupt request flag will be re- corded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow inter- rupt nesting. Once the stack is full, the interrupt request (except NMI) will not be acknowledged, even if the re- lated interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be pre- vented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the PC onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service pro- gram which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a an edge transition of INT0 or INT1 (ROM code option: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initial- ized by setting the Timer/Event Counter 0 interrupt re- quest flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is en- abled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related inter- rupt request flag (T0F) is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The A/D converter Interrupt is a Non-maskable interrupt (NMI) which occurs when an A/D conversion process has been completed and EOCB becomes ²0². The A/D converter interrupt is controlled by an EADI (bit 7 of the INTC0). When EADI= ²1², the A/D converter interrupt is enabled. If the EADI= ²0², the A/D converter interrupt is disabled. The A/D converter interrupt cannot be masked by disabling the EMI. After the interrupt is enabled, and if the A/D Conversion process has been completed (when EOCB becomes ²0²), a subroutine call to location 1CH occurs. If the stack is and if the A/D converter interrupt subroutine is serviced, the A/D converter interrupt ¢sre- turn address will be pushed into the stack, and the first return address in the stack will be flushed. It is important that at least one stack level is left available when using the A/D interrupt. The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is Register Bit No. Label Function INTC0 (0BH) 0 EMI Control the master (global) interrupt (1=enabled; 0=disabled) 1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled) 2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled) 3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) 4 EIF0 External interrupt 0 request flag (1=active; 0=inactive) 5 EIF1 External interrupt 1 request flag (1=active; 0=inactive) 6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) 7 EADI Control the A/D converter interrupt (NMI; 1=enable; 0=disable) INTC1 (1EH) 0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) 1 ETBI Control the time base interrupt (1=enabled; 0:disabled) 2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled) 3 ¾ Unused bit, read as ²0² 4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) 5 TBF Time base request flag (1=active; 0=inactive) 6 RTF Real time clock request flag (1=active; 0=inactive) 7 ¾ Unused bit, read as ²0² INTC Register |
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