Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DIFFERENTIAL RECEIVER TIMING REQUIREMENTS

t

PHZ

Disable Time High to Z

R

Figures 8, 9,

C

4.5

10

ns

t

PLZ

Disable Time Low to Z

3.5

8

ns

t

PZH

Enable Time Z to High

3.5

8

ns

t

PZL

Enable Time Z to Low

3.5

8

ns

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.

Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except

Note 4: ESD Rating: HBM (1.5 k

minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate,

the better the AC performance.

Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.

Note 8: Propagation delays are guaranteed by design and characterization.

Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.

Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.

Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge.

Applications Information

General application guidelines and hints may be found in the

following application notes: AN-808, AN-1035, AN-977,

AN-971, AN-918, and AN-903.

There are a few common practices which should be implied

when designing PCB for Bus LVDS signaling. Recom-

mended practices are:

•

Use at least 4 PCB board layer (Bus LVDS signals,

ground, power and TTL signals).

•

Keep drivers and receivers as close to the (Bus LVDS

port side) connector as possible.

•

Bypass each Bus LVDS device and also use distributed

bulk capacitance between power planes. Surface mount

capacitors placed close to power and ground pins work

best. Two or three high frequency, multi-layer ceramic

(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in paral-

lel should be used between each V

capacitors should be as close as possible to the V

Multiple vias should be used to connect V

planes to the pads of the by-pass capacitors.

In addition, randomly distributed by-pass capacitors

should be used.

•

Use the termination resistor which best matches the dif-

ferential impedance of your transmission line.

•

Leave unused Bus LVDS receiver inputs open (floating).

•

Isolate TTL signals from Bus LVDS signals

MEDIA (CONNECTOR or BACKPLANE) SELECTION:

•

Use controlled impedance media. The backplane and

connectors should have a matched differential imped-

ance.

TABLE 1. Functional Table

MODE SELECTED

DE

RE

DRIVER MODE

H

H

RECEIVER MODE

L

L

TRI-STATE MODE

L

H

LOOP BACK MODE

H

L

TABLE 2. Transmitter Mode

INPUTS

OUTPUTS

DE

D

IN

DO+

DO−

HL

L

H

HH

H

L

H

X

X

LX

Z

Z

TABLE 3. Receiver Mode

INPUTS

OUTPUT

RE

(RI+) – (RI−)

L

H

L

X

HX

Z

X = High or Low logic state

L = Low state

Z = High impedance state

H = High state

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