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ICS308R Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS308R Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 8 page ICS308 MDS 308 F 1 Revision 090704 Integrat ed Circuit Systems ● 5 25 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER Description The ICS308 is a versatile serially programmable, quad PLL clock source. The ICS308 can generate any frequency from 250 kHz to 200 MHz, and up to 6 different output frequencies simultaneously. The outputs can be reprogrammed on the fly, and will lock to a new frequency in 10 ms or less. Smooth transitions (in which the clock duty cycle remains roughly 50%) are guaranteed if the output divider is not changed. The device includes a PDTS pin which tri-states the output clocks and powers down the entire chip. The ICS308 default for non-programmed start-up are buffered reference clock outputs on all clock output pins. Features • Packaged in 20-pin SSOP (QSOP) • Operating voltage of 3.3 V • Highly accurate frequency generation • M/N Multiplier PLL: M = 1..2048, N = 1..1024 • Serially programmable: user determines the output frequency via a 3-wire interface • Eliminates need for custom quartz oscillators • Input crystal frequency of 5 - 27 MHz • Optional programmable on-chip crystal capacitors • Output clock frequencies up to 200 MHz • Reference clock output • Power down tri-state mode • Very low jitter Block Diagram C rystal O scillator GN D 2 3 VDD PDT S PLL2 PLL3 Divide Logic and Output Enable Control SCLK DATA CLK1 CLK9 CLK8 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 PLL4 PLL1 X2 Cry stal or cloc k input E xternal capacitors are required w ith a crystal input. X 1/IC LK STROBE |
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