IDT72V3654 datasheet(9/37 Pages) IDT

Part #	IDT72V3654

Description	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

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Manufacturer	IDT [Integrated Device Technology]

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IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

IDT72V3654L10(1)

IDT72V3654L15

IDT72V3664L10(1)

IDT72V3664L15

IDT72V3674L10(1)

IDT72V3674L15

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

fS

Clock Frequency, CLKA or CLKB

—

100

—

66.7

MHz

tCLK

Clock Cycle Time, CLKA or CLKB

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA

↑ and B0-B35 before CLKB↑

3—4

—

ns

tENS1

Setup Time,

CSA and W/RA before CLKA

↑; CSB and

4

—

4.5

—

ns

W/RB before CLKB

↑

tENS2

Setup Time, ENA, and MBA before CLKA

↑; ENB, and

3

—

4.5

—

ns

MBB before CLKB

↑

tRSTS

Setup Time,

MRS1, MRS2, PRS1, or PRS2 LOW before

5

—

5

—

ns

CLKA

↑orCLKB↑(2)

tFSS

Setup Time, FS0, FS1, FS2 before

MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

tBES

Setup Time, BE/

FWFT before MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

tSDS

Setup Time, FS0/SD before CLKA

↑

3—4

—

ns

tSENS

Setup Time, FS1/

SEN before CLKA

↑

3—4

—

ns

tFWS

Setup Time, BE/

FWFT before CLKA

↑

0—0

—

ns

tRTMS

Setup Time, RTM before

RT1; RTM before RT2

5—5

—

ns

tDH

Hold Time, A0-A35 after CLKA

↑and B0-B35 after CLKB↑

0.5

—

1

—

ns

tENH

Hold Time,

CSA, W/RA, ENA, and MBA after CLKA

↑; CSB,

0.5

—

1

—

ns

W/RB, ENB, and MBB after CLKB

↑

tRSTH

Hold Time,

MRS1, MRS2, PRS1 or PRS2 LOW after CLKA

↑

4—4

—

ns

or CLKB

↑(2)

tFSH

Hold Time, FS0, FS1, FS2 after

MRS1 and MRS2 HIGH

2

—

2

—

ns

tBEH

Hold Time, BE/

FWFT after MRS1 and MRS2 HIGH

2

—

2

—

ns

tSDH

Hold Time, FS0/SD after CLKA

↑

0.5

—

1

—

ns

tSENH

Hold Time, FS1/

SEN HIGH after CLKA

↑

0.5

—

1

—

ns

tSPH

Hold Time, FS1/

SEN HIGH after MRS1 and MRS2 HIGH

2

—

2

—

ns

tRTMH

Hold Time, RTM after

RT1; RTM after RT2

5—5

—

ns

tSKEW1(3)

Skew Time between CLKA

↑and CLKB↑ for EFA/ORA,

5

—

7.5

—

ns

EFB/ORB, FFA/IRA, and FFB/IRB

tSKEW2(3,4)

Skew Time between CLKA

↑ and CLKB↑ for AEA, AEB, AFA,12

—

12

—

ns

and

AFB

NOTES:

1. For 10ns speed grade: Vcc = 3.3V

± 0.15V; TA = 0° to +70°.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0

° C to +70° C; JEDEC JESD8-A compliant)

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