Application

20026902

Functional Description

The DS92LV1021A is an upgrade to the DS92LV1021. The

DS92LV1021A no longer has a power-up sequence require-

ment. Like the DS92LV1021, the DS92LV1021A is a 10-bit

Serializer designed to transmit data over a differential back-

plane at clock speeds from 16 to 40MHz. It may also be used

to drive data over Unshielded Twisted Pair (UTP) cable.

The DS92LV1021A can be used with any of National’s 10-bit

BLVDS Deserializers (DS92LV1212A for example) and has

three active states of operation: Initialization, Data Transfer,

and Resynchronization; and two passive states: Powerdown

and TRI-STATE.

The following sections describe each active and passive

state.

Initialization

Before data can be transferred, the Serializer must be initial-

ized. Initialization refers to synchronization of the Serializer’s

PLL to a local clock.

When V

TRI-STATE and internal circuitry is disabled by on-chip

power-on circuitry. When V

Serializer’s PLL begins locking to the local clock. The local

clock is the transmit clock, TCLK, provided by the source

ASIC or other device.

Once the PLL locks to the local clock, the Serializer is ready

to send data or SYNC patterns, depending on the levels of

the SYNC1 and SYNC2 inputs. The SYNC pattern is com-

posed of six ones and six zeros switching at the input clock

rate.

Control of the SYNC pins is left to the user. One recommen-

dation is a direct feedback loop from the LOCK pin. Under all

circumstances, the Serializer stops sending SYNC patterns

after both SYNC inputs return low.

Data Transfer

After initialization, the Serializer inputs DIN0–DIN9 may be

used to input data to the Serializer. Data is clocked into the

Serializer by the TCLK input. The edge of TCLK used to

strobe the data is selectable via the TCLK_R/F pin.

TCLK_R/F high selects the rising edge for clocking data and

low selects the falling edge. If either of the SYNC inputs is

high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored

regardless of the clock edge.

A start bit and a stop bit, appended internally, frame the data

bits in the register. The start bit is always high and the stop

bit is always low. The start and stop bits function as the

embedded clock bits in the serial stream.

Serialized data and clock bits (10+2 bits) are transmitted

frequency. For example, if TCLK is 40 MHz, the serial rate is

40 x 12 = 480 Mega bits per second. Since only 10 bits are

from input data, the serial “payload” rate is ten times the

TCLK frequency. For instance, if TCLK = 40 MHz, the pay-

load data rate is 40 x 10 = 400 Mbps. TCLK is provided by

the data source and must be in the range of 16 MHz to 40

MHz nominal.

connection. The outputs transmit data when the enable pin

(DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are

low. The DEN pin may be used to TRI-STATE the outputs

when driven low.

Ideal Crossing Point

The ideal crossing point is the best case start and stop point

for a normalized bit. Each ideal crossing point is found by

dividing the clock period by twelve--two clock bits plus ten

data bits. For example, a 40 MHz clock has a period of 25ns.

The 25ns divided by 12 bits is approximately 2.08ns. This

means that each bit width is approximately 2.08ns, and the

ideal crossing points occur every 2.08ns. For a graphical

representation, please see Figure 9.

Resynchronization

The Deserializer LOCK pin driven low indicates that the

Deserializer PLL is locked to the embedded clock edge. If

the Deserializer loses lock, the LOCK output will go high and

the outputs (including RCLK) will be TRI-STATE.

The LOCK pin must be monitored by the system to detect a

loss of synchronization, and the system must decide if it is

necessary to pulse the Serializer SYNC1 or SYNC2 pin to

resynchronize. There are multiple approaches possible. One

recommendation is to provide a feedback loop using the

www.national.com

2