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IDT72V295L15PFI Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72V295L15PFI Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 26 page 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18 Figure 4. Programmable Flag Offset Programming Sequence Figure 3. Offset Register Location and Default Values 17 0 007FH if LD is LOW at Master Reset, 03FFH if LD is HIGH at Master Reset DEFAULT VALUE FULL OFFSET (LSB) REGISTER 17 0 DEFAULT VALUE 007FH if LD is LOW at Master Reset, 03FFH if LD is HIGH at Master Reset 15 IDT72V295 (131,072 x 18-BIT) 16 15 16 EMPTY OFFSET (LSB) REGISTER 17 0 007FH if LD is LOW at Master Reset, 03FFH if LD is HIGH at Master Reset FULL OFFSET (LSB) REGISTER 17 0 DEFAULT VALUE DEFAULT VALUE 007FH if LD is LOW at Master Reset, 03FFH if LD is HIGH at Master Reset 15 IDT72V2105 (262,144 x 18-BIT) 16 15 16 EMPTY OFFSET (LSB) REGISTER 17 DEFAULT 0H 0 1 17 0 21 17 0 21 17 0 1 EMPTY OFFSET (MSB) REGISTER DEFAULT 0H FULL OFFSET (MSB) REGISTER DEFAULT 0H EMPTY OFFSET (MSB) REGISTER DEFAULT 0H FULL OFFSET (MSB) REGISTER 4668 drw 06 WCLK RCLK X X XX X X XX 4668 drw 07 LD 0 0 X 1 1 1 0 WEN 0 1 1 0 X 1 1 REN 1 0 1 X 0 1 1 X SEN 1 1 1 X X X 0 No Operation Write Memory Read Memory No Operation Parallel write to registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) Serial shift into registers: 34 bits for the 72V295 36 bits for the 72V2105 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) IDT72V295 IDT72V2105 Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. |
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