DS92LV1021AMSA datasheet(11/12 Pages) NSC

Part #	DS92LV1021AMSA

Description	16-40 MHz 10 Bit Bus LVDS Serializer

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Manufacturer	NSC [National Semiconductor (TI)]

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Serializer Pin Description

Pin Name

I/O

No.

Description

DIN

I

3–12

Data Input. TTL levels inputs. Data on these pins are loaded into a

10-bit input register.

TCLK_R/F

I

13

Transmit Clock Rising/Falling strobe select. TTL level input. Selects

TCLK active edge for strobing of DIN data. High selects rising

edge. Low selects falling edge.

DO+

O

22

+ Serial Data Output. Non-inverting Bus LVDS differential output.

DO−

O

21

− Serial Data Output. Inverting Bus LVDS differential output.

DEN

I

19

Serial Data Output Enable. TTL level input. A low, puts the Bus

LVDS outputs in TRI-STATE.

PWRDN

I

24

Powerdown. TTL level input. PWRDN driven low shuts down the

PLL and TRI-STATEs the outputs putting the device into a low

power sleep mode. This pin has an internal weak pull down.

TCLK

I

14

Transmit Clock. TTL level input. Input for 16 MHz–40 MHz

(nominal) system clock.

SYNC

I

1, 2

Assertion of SYNC (high) for at least 1024 synchronization symbols

to be transmitted on the Bus LVDS serial output. Synchronization

symbols continue to be sent if SYNC continues asserted. TTL level

input. The two SYNC pins are ORed.

DVCC

I

27, 28

Digital Circuit power supply. DVCC voltage level should be identical

to the AVCC voltage level.

DGND

I

15, 16

Digital Circuit ground. Ground potential should be the same as

AGND.

AVCC

I

17, 26

Analog power supply (PLL and Analog Circuits). AVCC voltage

level should be identical to the DVCC voltage level.

AGND

I

18, 25, 20, 23

Analog ground (PLL and Analog Circuits). Ground potential should

be the same as DGND.

Truth Table

DIN (0–9)

TCLK_R/F

TCLK

SYNC1/SYNC2

DEN

PWRDN

DO+

DO−

XXX

X

0

Z

XXX

X

0

1

Z

X

SYSTEM CLK

1

∼

1

SYNC PTRN

SYNC PTRN*

DATA

1

L

0

1

DATA (0–9)

DATA (0–9)*

DATA

0

K

0

1

DATA (0–9)

DATA (0–9)*

RI

RI−

RCLK_R/F

REFCLK

REN

PWRDN

RCLK

LOCK

XXX

X

0

Z

X

0**

1

Z

SYNC PTRN

SYNC PTRN*

X

SYSTEM CLK

1

CLK

1†

DATA (0–9)

DATA (0–9)*

1

SYSTEM CLK

1

L

0

DATA (0–9)

DATA (0–9)*

0

SYSTEM CLK

1

K

0

∼ Pulse 5-bits

* Inverted

†Must be 1 before SYNC PTRN starts

** Device must be locked first

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