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IDT72V805L10PFI Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V805L10PFI Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 26 page 2 IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS TQFP (PK128-1, ORDER CODE: PF) TOP VIEW FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs contained in these devices has an 18-bit input and output port. Each input port is controlled by a free-running clock (WCLK), and an input enable pin ( WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port of each FIFO bank is controlled by another clock pin (RCLK) and another enable pin ( REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual- clock operation. An Output Enable pin ( OE) is provided on the read port of each FIFO for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready ( EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty ( PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin ( LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. These devices are depth expandable using a Daisy-Chain technique or First Word Fall Through (FWFT) mode. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using IDT’s high-speed submicron CMOS technology. VCC LDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PAFA RXIA FFA WXOA/HFA RXOA QA0 QA1 GND QA2 QA3 VCC QA4 GND QA5 QA6 QA7 QA8 GND DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PAEB FLB WCLKB WENB WXIB VCC PAFB RXIB FFB WXOB/HFB RXOB 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 OEA RSA VCC GND EFA QA17 QA16 GND QA15 VCC QA14 QA13 GND QA12 QA11 VCC QA10 QA9 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 RCLKB RENB LDB OEB RSB VCC GND EFB INDEX GND 4295 drw 02 DESCRIPTION (CONTINUED) |
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