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K7D803671B-HC35 Datasheet(PDF) 10 Page - Samsung semiconductor

Part # K7D803671B-HC35
Description  256Kx36 & 512Kx18 SRAM
Download  16 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K7D803671B-HC35 Datasheet(HTML) 10 Page - Samsung semiconductor

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Rev 4.0
256Kx36 & 512Kx18 SRAM
- 10
January. 2002
K7D801871B
K7D803671B
AC CHARACTERISTICS(For both AC test condition 1 and 2)
NOTE : 1. See AC Test Output Load figure
2. Design target is 0ns
Parameter
Symbol
-33
-30
-25
Unit
Note
Min
Max
Min
Max
Min
Max
Clock Cycle Time
tKHKH
3.0
-
3.3
-
4.0
-
ns
Clock High Pulse Width
tKHKL
1.3
-
1.5
-
1.7
-
ns
Clock Low Pulse Width
tKLKH
1.3
-
1.5
-
1.7
-
ns
CQ High Pulse Width
tCHCL
tKHKL-0.1
tKHKL+0.1
tKHKL-0.2
tKHKL+0.2
tKHKL-0.3
tKHKL+0.3
ns
CQ Low Pulse Width
tCLCH
tKLKH-0.1
tKLKH+0.1
tKLKH-0.2
tKLKH+0.2
tKLKH-0.3
tKLKH+0.3
ns
Clock to Echo Clock(CQ) High
tKXCH
0.5
1.7
0.5
1.9
0.5
2.0
ns
1
Clock to Echo Clock(CQ) Low
tKXCL
0.5
1.7
0.5
1.9
0.5
2.0
ns
Echo Clock to Output Valid
tCHQV/tCLQV
-
0.2
-
0.2
-
0.25
ns
1,2
Echo Clock to Output Hold
tCHQX/tCLQX
-0.2
-
-0.2
-
-0.25
-
ns
1
Echo Clock to Output High-Z
tCHQZ/tCLQZ
0.2
0.2
0.25
ns
1
G Low to Output Low-Z
tGLQX
0.5
-
0.5
-
0.5
-
ns
1
G High to Output High-Z
tGHQZ
-
2.1
-
2.3
-
2.5
ns
1
G Low to Output Valid
tGLQV
-
2.1
-
2.3
-
2.5
ns
1
Address Setup Time
tAVKH
0.4
-
0.4
-
0.5
-
ns
Address Hold Time
tKHAX
0.4
-
0.4
-
0.5
-
ns
Burst Control Setup Time
tBVKH
0.4
-
0.4
-
0.5
-
ns
Burst Control Hold Time
tKHBX
0.4
-
0.4
-
0.5
-
ns
Data Setup Time
tDVKH
0.4
-
0.4
-
0.5
-
ns
Data Hold Time
tKHDX
0.4
-
0.4
-
0.5
-
ns
AC CHARACTERISTICS(For AC test condition 1)
NOTE : 1. See AC Test Output Load figure
2. Design target is 0ns
Parameter
Symbol
-37
-35
Unit
Note
Min
Max
Min
Max
Clock Cycle Time
tKHKH
2.7
-
2.8
-
ns
Clock High Pulse Width
tKHKL
1.3
-
1.3
-
ns
Clock Low Pulse Width
tKLKH
1.3
-
1.3
-
ns
CQ High Pulse Width
tCHCL
tKHKL-0.1
tKHKL+0.1
tKHKL-0.1
tKHKL+0.1
ns
CQ Low Pulse Width
tCLCH
tKLKH-0.1
tKLKH+0.1
tKLKH-0.1
tKLKH+0.1
ns
Clock to Echo Clock(CQ) High
tKXCH
0.5
1.7
0.5
1.7
ns
1
Clock to Echo Clock(CQ) Low
tKXCL
0.5
1.7
0.5
1.7
ns
Echo Clock to Output Valid
tCHQV/tCLQV
-
0.2
-
0.2
ns
1,2
Echo Clock to Output Hold
tCHQX/tCLQX
-0.2
-
-0.2
-
ns
1
Echo Clock to Output High-Z
tCHQZ/tCLQZ
0.2
0.2
ns
1
G Low to Output Low-Z
tGLQX
0.5
-
0.5
-
ns
1
G High to Output High-Z
tGHQZ
-
2.1
-
2.1
ns
1
G Low to Output Valid
tGLQV
-
2.1
-
2.1
ns
1
Address Setup Time
tAVKH
0.4
-
0.4
-
ns
Address Hold Time
tKHAX
0.4
-
0.4
-
ns
Burst Control Setup Time
tBVKH
0.4
-
0.4
-
ns
Burst Control Hold Time
tKHBX
0.4
-
0.4
-
ns
Data Setup Time
tDVKH
0.4
-
0.4
-
ns
Data Hold Time
tKHDX
0.4
-
0.4
-
ns


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