Rev 4.0

256Kx36 & 512Kx18 SRAM

- 5 -

January. 2002

K7D801871B

K7D803671B

Interleaved Burst

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0

0

1

1

0

1

0

1

0

0

1

1

1

0

1

0

1

1

0

0

0

1

0

1

1

1

0

0

1

0

1

0

TRUTH TABLE

NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".

- K & K are complementary.

K

G

B1

B2

B3

DQ

Operation

L

X

X

X

X

Hi-Z

Clock Stop

↑

X

H

L

X

Hi-Z

No Operation, Pipeline High-Z

↑

L

L

H

H

DOUT

Load Address, Single Read

↑

L

L

H

L

DOUT

Load Address, Double Read

↑

X

L

L

H

DIN

Load Address, Single Write

↑

X

L

L

L

DIN

Load Address, Double Write

↑

X

H

H

X

B

Increment Address, Continue

BURST SEQUENCE TABLE

Linear Burst Mode

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

0

0

1

1

0

1

0

1

0

1

1

0

1

0

1

0

1

1

0

0

0

1

0

1

1

0

0

1

1

0

1

0