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NCP3134 Datasheet(PDF) 11 Page - ON Semiconductor |
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NCP3134 Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 13 page NCP3134 www.onsemi.com 11 PROTECTIONS Under Voltage Lockout (UVLO) There is under -voltage lock out protection (UVLO) for both VIN and VDD in NCP3134, which has a typical trip threshold voltage 2.8 V and trip hysteresis 75 mV for VDD and 130 mV for VIN. If UVLO is triggered, the device resets and waits for the voltage to rise up over the threshold voltage and restart the part. Please note this protection function DOES NOT trigger the fault counter to latch off the part. Over Voltage Protection (OVP) When feedback voltage is above 17% (typical) of nominal voltage for over 1.7 ms blanking time, an OV fault is set. In this case, the converter de−asserts the PGD signal and performs the over−voltage protection function. The top gate drive is turned off and the bottom gate drive is turned on to discharge the output. The bottom gate drive will be turned off until VFB drops below the UVP threshold. The device enters a high−impedance state. This protection is latched. Under Voltage Protection (UVP) Output under−voltage protection works in conjunction with the current protection described in the Over−current Protection sections. An UVP circuit monitors the feedback voltage to detect under−voltage event. The under−voltage limit is 17% (typical) below of nominal voltage at FB pin. If the feedback voltage is below this threshold over 6.5 ms, an UV fault is set and both the high−side and the low−side FETs turn off . This protection is latched. Power Good Monitor (PGD) NCP3134 provides window comparator to monitor the output voltage at FB pin. When the output voltage is within ±17% of regulation voltage, the power good pin outputs a high signal. Otherwise, PGD stays low. The PGD pin is open drain 5 mA pull down output. During startup, PGD stays low until the feedback voltage is within the specified range for about 0.2 ms. If feedback voltage falls outside the tolerance band, the PG pin goes low after 10 ms delay. The PGD pin de−asserts as soon as the EN pin is pulled low or an under−voltage event on VDD is detected. Over Current Protection (OCP) NCP3134 provides both high−side and low−side MOSFET current limiting. When the current through the high−side FET exceeds 5.2 A, the high−side FET turns off and the low−side FET turns on until next PWM cycle. An over−current counter is triggered and starts to increment each occurrence of an over−current event. Both the high−side and the low−side FETs turn off when the OC counter reaches four. The OC counter resets if the detected current is less than 5.2 A after an OC event. Another set of over−current circuitry monitors the current flowing through the low−side FET. If the current through the low−side FET exceeds 7.8 A, the over−current protection is enabled and immediately turns off both the high−side and the low−side FETs. The device is fully protected against over−current during both on−time and off−time. This protection is latched. Pre−Bias Startup In some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter’s output capacitors may have residual charge on them or the converter’s output may be held up by a low current standby power supply. NCP3134 supports pre−bias start up by holding low−side FETs off until soft start ramp reaches the FB pin voltage. Thermal Shutdown The NCP3134 protects itself from over heating with an internal thermal monitoring circuit. When the die temperature goes beyond a threshold value 160 °C, both the high−side and the low−side FETs turn off until the temperature falls 10 °C below of the threshold value. Then the converter restarts. Application Note For higher output voltage application cases (Vout = 3.3 V), choose the inductor value not to be lower than 1 mH to avoid over-current protection being triggered by inductor current ripple. For VIN=5V and VOUT=3.3V case, add a voltage divider between VIN and EN to ensure that the part can start up without triggering UVP. Use the following figure as design reference for schematics. For other lower output voltage cases, it is not necessary to add this divider. PGND EN 3.6 k W 10 k W VIN = 5 V Output current at the transition between CCM and DCM can be calculated in the following equation: Io = 0.5 x (Vin−Vo) x Vo/Vin/fs/L Io − output current at boundary of CCM and DCM; Vin − input voltage; Vo − output voltage; fs − switching frequency; L − inductor |
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