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LT1619ES8 Datasheet(PDF) 7 Page - Linear Technology |
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LT1619ES8 Datasheet(HTML) 7 Page - Linear Technology |
7 / 20 page 7 LT1619 1619fa OPERATIO Inductor The value of the inductor is usually selected so that the peak-to-peak ripple current is less than 30% of the maxi- mum inductor current. The inductor should be able to handle the maximum inductor current at full load without saturation. Powder iron cores are not suitable for high frequency switch mode power supply applications be- cause of their high core losses. Ferrite cores have very low core losses and are the material of choice for high fre- quency DC/DC converters. Power MOSFET Driver The LT1619 is capable of driving a low side N-channel power MOSFET with up to 60nC of total gate charge (Qg). An external driver is recommended for MOSFETs with greater than 80nC of total gate charge. The peak gate drive current varies from 0.5A with VDRV = 2.5V to 1.2A with VDRV = 10V. The MOSFET driver is capable of charging the gate of the power MOSFET to within 350mV of the upper gate drive supply rail (DRV). It can also pull the gate of the MOSFET to within 100mV of ground during turnoff. The upper supply rail of the gate drive is brought out as a device pin (DRV) for design flexibility. In a boost converter design, the DRV pin can be tied to the converter output if the minimum input voltage is insufficient to fully enhance the power MOSFET. During start-up, the MOSFET is driven with a gate voltage starting from VIN – VD (VD is the forward voltage of the rectifying diode). As the output voltage rises, the gate drive also increases until steady state is reached. If the steady-state converter output voltage exceeds the maximum allowable gate source voltage and the input voltage is sufficient to enhance the MOSFET, the DRV pin is tied to the input supply. For a SEPIC converter, the DRV pin can be tied to the input or diode OR’ed from the input and the output (Figure 4). Figure 4. SEPIC Converter with Diode OR’ed Gate Drive Supply or less than the number specified in Table 1 are accept- able. The maximum duty cycle is essentially unaffected by synchronization. The device will go into shutdown mode if the S/S pin voltage stays below the shutdown threshold of 0.45V for more than 33 µs. This shutdown delay is reset whenever the S/S pin voltage rises above the shutdown threshold. Applying a logic low signal at the S/S pin causes the gate drive output to go low. Although all circuits in the LT1619 are disabled, the pull-down circuit in the MOSFET buffer is still biased on. It is capable of shunting any leakage or transient current at the GATE pin to ground, eliminating the need for an external bleed resistor. The LT1619 con- sumes 15 µA in shutdown. The LT1619 is guaranteed to start with a minimum VIN of 1.85V. Comparator A2 senses the input voltage and gen- erates an undervoltage lockout (UVLO) signal if VIN falls below this minimum. While in undervoltage lockout, VC is pulled low and the LT1619 stops switching. The supply current drawn by the device falls to 140 µA. Table 1. Maximum Allowable Rise Time of Synchronization Pulse. Rise Time Can Be Slower if Clock Amplitude is Higher SYNCHRONIZATION MAXIMUM ALLOWABLE AMPLITUDE (V) RISE TIME (ns) 1.2 120 1.5 220 2.0 350 2.5 470 3.0 530 DRV VIN VOUT RS 1619 F03 LT1619 GND • • + APPLICATIO S I FOR ATIO |
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