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LP3883ESX-1.8 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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LP3883ESX-1.8 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 12 page  Application Hints (Continued) F p =1/(2X π X 5 X .047 X 10E-6) = 677 kHz This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and bandwidth, there are usually values of small capacitors which can seriously re- duce phase margin. If the capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to "decouple" them from the regulator output. INPUT CAPACITOR The input capacitor must be at least 4.7 µF, but can be increased without limit. It’s purpose is to provide a low source impedance for the regulator input. Ceramic capaci- tors work best for this, but Tantalums are also very good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application where temperatures go below about 10˚C. BIAS CAPACITOR The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended). BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 6V to assure proper operation of the part. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 4V. SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regula- tor. Pin S/D must be actively terminated through a pull-up resistor (10 k Ω to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction tem- perature must be within the range specified under operating conditions. The total power dissipation of the device is given by: P D =(VIN−VOUT)IOUT+(VIN)IGND where I GND is the operating ground current of the device. The maximum allowable temperature rise (T Rmax) depends on the maximum ambient temperature (T Amax) of the appli- cation, and the maximum allowable junction temperature (T Jmax): T Rmax =TJmax−TAmax The maximum allowable value for junction to ambient Ther- mal Resistance, θ JA, can be calculated using the formula: θ JA =TRmax /PD These parts are available in TO-220 and TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θ JA calculated above is ≥ 60 ˚C/W for TO-220 package and ≥ 60 ˚C/W for TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θ JA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θ JA will be same as shown in next section for TO263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θ HA ≤θ JA − θ CH − θ JC. In this equation, θ CH is the thermal resistance from the case to the surface of the heat sink and θ JC is the thermal resis- tance from the junction to the surface of the case. θ JC is about 3˚C/W for a TO220 package. The value for θ CH de- pends on method of attachment, insulator, etc. θ CH varies between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown, 2˚C/W can be assumed. HEATSINKING TO-263 PACKAGE The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. The graph below shows a curve for the θ JA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. 20062425 FIGURE 1. θ JA vs Copper (1 Ounce) Area for TO-263 package www.national.com 9 |
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